There is a continuing trend within the microelectronics industry to incorporate more circuitry having greater complexity on a single integrated circuit (IC) chip. Maintaining this trend generally entails shrinking the size of individual devices within the circuit by reducing the critical dimensions (CDs) of device elements along with the pitch (the CD of such an element plus the spacing between elements). Microlithography tooling and processing techniques play an important role in resolving the features necessary to fabricate devices and, accordingly, are continually under development to meet industry milestones relating to the CD and pitch characteristic of each new technology generation.
High numerical aperture (NA) projection stepper/scanner systems in combination with advanced photoresist processes now are capable of routinely resolving complex patterns that include isolated and dense resist features having CDs and pitches, respectively, well below the exposure wavelength. However, to meet the requirements of device design rules which continue to push the resolution limits of existing processes and tooling, other more specialized techniques have been developed to further enhance resolution. These include double patterning technology (DPT) techniques in which device patterns having potentially optically unresolvable features are decomposed into two or more complementary, and more easily resolvable patterns, each containing features with larger CDs and/or a relaxed pitch.
A router is an electronic design automation (EDA) tool used to convert logical designs into manufacturable layouts, and to connect the physical devices in the layout with metal lines. In DPT processes, a double patterning compliant router may be configured with a processing engine, including appropriate software, to decompose patterns and features into separate patterns, with each pattern being implemented in its own mask. In order to comply with manufacturing requirements, each pattern must satisfy its own single patterning rules, also called “same mask rules” or “same color rules”, that is, a set of rules defining the limit of single pattern resolution for critical dimensions manufacturable by the foundry.
The same color rules are also called color rules for simplicity. A typical same color rule set includes minimum spacing requirements for tip-to-tip, tip-to-side, and side-to-side critical dimensions. The same color rules are determined by the manufacturing technology used by the foundry.
In accordance with a typical IC manufacturing process, if a particular design input includes two structures or features which result in a layout in which the two features are spaced apart by less than the CD specified in the color rule space, the router ensures that the generated routing structures can be decomposed into two masks, where the space between each pair of structures in the same mask is equal to or larger than the critical spaces specified by the same color rules.
Double patterning technologies necessitate a zero odd cycle requirement on double patterning routing layouts rendered by DPT compliant routers in order to ensure the manufacturability of the underlying IC designs. To accomplish this, a router must be capable of generating a decomposable layout for all IC design components and features. Ideally, a DPT compliant router should theoretically be qualified for every possible design configuration for each color rule set.
As a practical matter, routers are typically qualified, or stress tested, based on a specified color rule space and a specified design space. In this context, the term “color rule space” typically refers to a set of color rules associated with a particular manufacturing technology or methodology, and includes a specific numerical value for each color rule parameter such as tip-to-tip spacing, side-to-side spacing, and other critical physical dimensions. The term “design space” refers to a limited set of predetermined test designs useful in assessing the robustness of a router's DPT compliance and decomposition processing software and architecture.
When a router's processing engine generates (or “exposes”) decomposition errors during the qualification, the errors are fed back to the development team to reconfigure the processing engine until an odd cycle clean output condition is achieved; that is, until application of the color rule space to the design rule space yields zero odd cycles (decomposition errors). However, given the relatively limited scope of the design space vis-à-vis the universe of possible design configurations encountered in the ordinary course of manufacturing IC devices, the confidence level associated with presently known router qualification processes is unsatisfactorily low.